FIG. 18 shows the driving circuit for the liquid-crystal display apparatus by the active matrix liquid-crystal panels to be used in the liquid-crystal TV apparatus. Such a circuit as described hereinabove is described in, for example, Japanese Patent Application Laid-Open Publication Tokkaisho No. 57-41078.
In the same drawing, the liquid-crystal panel 1 of the active matrix type has n column of picture elements in the X direction and m row of picture elements in the Y direction. The TFTs (thin film transistors) la composed of m.times.n amorphous silicons (a-Si) and the liquid-crystal electrodes 1b are connected in matrix shape as shown with the respective rows G1, G2, ... Gm and the respective columns D1, D2, Dn being respectively connected with the row driver 2 and the column driver 3. The row driver is composed of the m stage of shift register 2a and output circuit 2b. The column driver is composed of the n stage of shift register 3a, the sampling hold circuit 3b and the output circuit 3c. The synchronization controlling circuit 4 generates the first and second start pulses ST1 and ST2 and the first and second clock pulses CP1 and CP2 in accordance with the horizontal synchronizing signal H.sub.P and the vertical synchronizing signal V.sub.P.
The first start pulse ST1 synchronized with the vertical synchronizing signal and the first clock pulse CP1 synchronized with the horizontal synchronizing signal are fed into the shift register 2a, the voltage waveforms shifted 1H (1 horizontal period) by 1H are applied upon each row G1, G2, ... . The TFTs 1a of each line are sequentially turned on in the horizontal retrace section by the voltage waveform to apply the liquid-crystal driving voltage upon each picture element.
On the other hand the column driver repeats the same operation in each 1H section.
The second start pulse ST2 synchronized with the horizontal synchronizing signal and the second clock pulse of the frequency of the period .tau.=T5/n are fed into the shift register 3a, the pulse sequentially shifted .tau. by .tau. is output to the output of each stage of the shift register 3a. Each stage of the sample holding circuit 3b is controlled by the output of the shift register of each of the corresponding stages, the voltage value of the image signal is sampled by the falling of the output to hold it till the sampling time (for 1H). The output circuit 3c receives the output of the sampling hold circuit to buffer-amplify to drive the column electrode.
The shift register in the above-described driving circuit is of a construction as shown in FIG. 19. As the transfer of the data, as apparent from FIG. 19 (the drawing shows one stage portion), is performed through the sequential switching operation of four transistors per stage of the shift register by clock .phi.,.phi., the delay time per stage of transistor is required to be within one fourth of the clock period for the operation. Namely, as the comparatively fast switching speed is required for the transistor, the transistor of the slow switching speed like the a-Si TFT in use for the liquid-crystal panel 1 can not be used.